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general description the DS1863 controls and monitors all the burst-mode transmitter and video receiver biasing functions for a passive optical network (pon) triplexer. it has an apc loop with tracking-error compensation that provides the reference for the laser-driver? bias current, and a tem- perature indexed lookup table (lut) that controls the modulation current. it continually monitors for high output current, high bias current, and low and high transmit power with its internal fast comparators to ensure that laser shutdown for eye safety requirements are met with- out adding external components. five adc channels monitor v cc , internal temperature, and three external monitor inputs (mon1?) that can be used to meet trans- mitter and receive monitoring requirements. applications bpon, gpon and gepon, burst-mode transmitters laser control and monitoring broadband local access features meets bpon, gpon, and gepon timing requirements for burst-mode transceivers bias current control provided by apc loop with tracking error compensation modulation current is controlled by a temperature-indexed lookup table supports 0db, -3db, -6db power leveling settings with no additional calibration internal direct-to-digital temperature sensor five analog monitor channels: temperature, v cc , mon1, mon2, and mon3 comprehensive fault management system with maskable laser shutdown capability two-level password access to protect calibration data 120 bytes of password 1 (pw1) protected nonvolatile memory 128 bytes of password 2 (pw2) protected nonvolatile memory i 2 c-compatible interface for calibration and monitoring operating voltage: 2.85v to 5.5v operating temperature: -40? to +95? 16-pin lead-free tssop package DS1863 burst-mode pon controller with integrated monitoring ______________________________________________ maxim integrated products 1 rev 0; 10/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. +denotes lead-free package. t&r denotes tape-and-reel. ordering information part temp range pin-package DS1863e+ -40 c to +95 c 16 tssop DS1863e+t&r -40 c to +95 c 16 tssop 16 15 14 13 12 11 10 1 2 3 4 5 6 7 v cc bmd mod bias tx-f n.c. tx-d ben top view gnd mon3 mon2 scl sda 9 8 mon1 gnd fetg tssop (173 mils) DS1863 + pin configuration
DS1863 burst-mode pon controller with integrated monitoring 2 _____________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -40 c to +95 c, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage on v cc , sda and scl pin relative to ground....................................................................-0.5v to 6v voltage on ben, tx-d, tx-f, mon1 mon3, bmd relative to ground ...............................-0.5v to v cc + 0.5v (subject to not exceeding +6v) operating temperature range ...........................-40 c to +95 c programming temperature range .........................0 c to +70 c storage temperature range .............................-55 c to +125 c soldering temperature ...................see j-std-020 specification parameter symbol conditions min typ max units supply voltage v cc (note 1) +2.85 5.5 v high-level input voltage (sda, scl, ben) v ih:1 0.7 x v cc v cc + 0.3 v low-level input voltage (sda, scl, ben) v il:1 -0.3 0.3 x v cc v high-level input voltage (tx-d) v ih:2 2.0 v cc + 0.3 v low-level input voltage (tx-d) v il:2 -0.3 0.8 v electrical characteristics (v cc = +2.85v to +5.5v; t a = -40 c to +95 c, unless otherwise noted.) parameter symbol conditions min typ max units supply current i cc (notes 1, 2) 5 7 ma output leakage (sda, tx-f) i lo 1a i ol = 4ma 0.4 low-level output voltage (sda, tx-f, fetg) v ol i ol = 6ma 0.6 v high-level output voltage (fetg) v oh i oh = 4ma (note 2) v cc 0.4 v fetg before recall (note 3) 10 100 na input leakage current (scl, ben, tx-d) i li:1 1a digital power-on reset pod 1.0 2.2 v analog power-on reset poa 2.1 2.75 v
DS1863 burst-mode pon controller with integrated monitoring _____________________________________________________________________ 3 analog input characteristics (bmd) (v cc = +2.85v to +5.5v ; t a = -40 c to +95 c , unless otherwise noted.) parameter symbol conditions min typ max units bmd-full-scale voltage range v apc (note 4) 2.5 v resolution (note 4) 8 bits v apc error (note 5), t a = 25 c -1.75 +1.75 %fs v apc integral nonlinearity -1 +1 lsb v apc differential nonlinearity -1 +1 lsb v apc temp drift -2.5 +2.5 %fs input resistance 35 50.0 65 k ? analog output characteristics (v cc = +2.85v to +5.5v; t a = -40 c to +95 c, unless otherwise noted.) parameter symbol conditions min typ max units bias current i bias (note 1) 1.2 ma i bias shutdown current i b ia s : of f 10 100 na voltage at i bias 0.7 1.2 1.4 v mod full-scale voltage v mod (note 6) 1.25 v mod output impedance (note 7) 3.14 k ? v mod error (note 8), t a = 25 c -1.25 +1.25 %fs v mod integral nonlinearity -1 +1 lsb v mod differential nonlinearity -1 +1 lsb v mod temperature drift -2 +2 %fs control loop and quick-trip timing characteristics (v cc = +2.85v to +5.5v; t a = -40 c to +95 c, unless otherwise noted.) parameter symbol conditions min typ max units first bmd sample following ben t first (note 9) remaining updates during ben t rep (note 9) ben high time t ben:high 420 ns ben low time t ben:low 96 ns bias and mod t off 5s bias and mod t on 5s fetg turn-on delay t fetg:on 5s fetg turn-off delay t fetg:off 5s binary search time t search (note 10) 5 13 bias samples adc round-robin time t rr 65 ms
DS1863 burst-mode pon controller with integrated monitoring 4 _____________________________________________________________________ nonvolatile memory characteristics (v cc = +2.85v to +5.5v, unless otherwise noted.) parameter symbol conditions min typ max units eeprom write cycles +70 c 50,000 i 2 c ac electrical characteristics (v cc = +2.85v to +5.5v, t a = -40 c to +95 c, unless otherwise noted, see figure 9.) parameter symbol conditions min typ max units scl clock frequency f scl (note 11) 0 400 khz clock pulse width low t low 1.3 s clock pulse width high t high 0.6 s bus free time between stop and start condition t buf 1.3 s start hold time t hd:sta 0.6 s start setup time t su:sta 0.6 s data-in hold time t hd:dat 0 0.9 s data-in setup time t su:dat 100 ns rise time of both sda and scl signals t r (note 12) 20 + 0.1c b 300 ns fall time of both sda and scl signals t f (note 12) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 s capacitive load for each bus line c b (note 12) 400 pf eeprom write time t w (note 13) 20 ms note 1: all voltages are referenced to ground. currents into the ic are positive and out of the ic are negative. note 2: digital inputs are at rail. fetg is disconnected sda = scl = 1. note 3: see safety shutdown (fetg) output section for details. note 4: eight ranges allow the full-scale range to change from 625mv to 2.5v. note 5: this specification applies to the expected full-scale value for the selected range. see comp ranging byte for available full- scale ranges. note 6: eight ranges allow the full-scale range to change from 312-5mv to 1.25v. note 7: the output impedance of the DS1863 is proportional to its scale setting. for instance, if using the 1/2 scale, the output impedance would be 1.5k ? . note 8: this specification applies to the expected full-scale value for the selected range. see mod ranging byte for available full- scale ranges. note 9: see apc/quick-trip sample timing section for details. note 10: assuming an appropriate initial step is programmed that would cause the power to exceed the apc set point within 4 steps, the bias current will be within 1% within the time specified by the binary search time. note 11: i 2 c interface timing shown is for fast-mode (400khz) operation. this device is also backward-compatible with i 2 c standard- mode timing. note 12: c b total capacitance of one bus line in picofarads. note 13: eeprom write begins after a stop condition occurs. note 14: guaranteed by design.
DS1863 burst-mode pon controller with integrated monitoring typical operating characteristics ( v cc = 3.3v; t a = +25 c, unless otherwise noted.) 2.50 2.95 2.80 2.65 3.10 3.25 3.40 3.55 3.70 3.85 4.00 2.85 3.85 3.35 4.35 4.85 5.35 supply current vs. supply voltage DS1863 toc01 v cc (v) supply current (ma) sda = scl = v cc +95 c -40 c +25 c 3.00 3.15 3.10 3.05 3.25 3.20 3.45 3.40 3.35 3.30 3.50 -40 -20 0 20 40 60 80 100 supply current vs. temperature DS1863 toc02 temperature ( c) supply current (ma) v cc = 2.85v v cc = 5.5v sda = scl = v cc -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 100 50 150 200 250 mod dnl DS1863 toc03 mod input code (dec) mod dnl (lsb) -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 100 50 150 200 250 mod inl DS1863 toc04 mod input code (dec) mod inl (lsb) 0 20 10 40 30 60 50 70 90 80 100 001 010 000 011 100 101 110 111 calculated and desired % change in v mod vs. mod ranging DS1863 toc05 mod ranging value (dec) change in v mod (%) desired value calculated value 0 20 10 40 30 60 50 70 90 80 100 desired and calculated change in v bmd vs. comp ranging DS1863 toc06 comp ranging (dec) change in v bmd (%) 001 010 000 011 100 101 110 111 desired value calculated value -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 01.0 0.5 1.5 2.0 2.5 mon1? dnl DS1863 toc07 mon1? input voltage (v) mon1? dnl (lsb) using factory-programmed full-scale value of 2.5v -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 01.0 0.5 1.5 2.0 2.5 mon1 3 inl DS1863 toc08 mon1 3 input voltage (v) mon1 3 inl (lsb) using factory-programmed full-scale value of 2.5v -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 100 50 150 200 250 v bmd inl vs. apc index DS1863 toc09 apc index (dec) v bmd inl (lsb) _____________________________________________________________________ 5
DS1863 burst-mode pon controller with integrated monitoring 6 _____________________________________________________________________ pin description pin name description 1 ben burst enable input. triggers the sampling of the apc and quick-trip monitors. 2 tx-d transmit disable input. disables bias and mod outputs. 3 n.c. no connection 4 tx-f transmit fault output. open-drain. 5 fetg output to fet gate. signals an external n or p channel mosfet to enable/disable the laser s current. 6 sda i 2 c serial data i/o 7 scl i 2 c serial clock input 8 gnd ground 9 mon1 10 mon2 11 mon3 external analog inputs. the voltage at these pins is digitized by the internal analog-to-digital converter and can be read through the i 2 c interface. alarm and warning values can be assigned to interrupt the processor based on the adc result. 12 gnd ground 13 bias bias current output. this current dac generates the bias current reference for the max3643. 14 mod modulation output voltage. this 8-bit voltage output has 8 full-scale ranges from 1.25v to 0.3125v. this pin is connected to the max3643 s vmset input to control the modulation current. 15 bmd monitor diode input (feedback voltage, transmit power monitor) 16 v cc power supply input
DS1863 burst-mode pon controller with integrated monitoring _____________________________________________________________________ 7 bmd ben mon2 mon1 mon3 scl sda gnd v cc tx-d bias mod fetg tx-f hbias quick trip limit htxp quick trip limit ltxp quick trip limit apc setpoint from tracking error table latch enable v cc temp sensor i 2 c interface sample control 8-bit dac w/scaling digital apc integrator 13-bit dac analog mux modulation lookup table (table 04h) 8-bit dac w/scaling max bias quicktrip interrupt mask interrupt latch interrupt mask interrupt latch power on analog v cc > v poa nonmaskable interrupt 13-bit adc DS1863 memory organization sram reset right shift table 01h eeprom pw1 user memory and alarm traps table 02h eeprom configuration and calibration table 03h eeprom pw2 user memory lower memory eeprom/sram adc config/results system status bits alarm/warning comparison results/thresholds table 04h eeprom modulation lut table 05h eeprom tracking error lut digital limit comparator for adc results DS1863 mux mux mux block diagram
DS1863 burst-mode pon controller with integrated monitoring 8 _____________________________________________________________________ detailed description the DS1863 integrates the control and monitoring func- tionality required to implement a pon system using maxim s max3643 compact burst mode laser driver. the compact laser driver solution offers a considerable cost benefit by integrating control and monitoring fea- tures in low power cmos process, while leaving only the high speed portions to the laser driver ic. apc control bias current is controlled by an average power control (apc) loop. the apc loop uses digital techniques to overcome the difficulties associated with controlling burst mode systems. the apc loop s feedback is the monitor diode (bmd) current, which is converted to a voltage using an exter- nal resistor. the feedback voltage is compared to an 8- bit scaleable voltage reference, which determines the apc set point of the system. scaling of the reference voltage along with the modulation output can be uti- lized to implement gpon power leveling. the DS1863 has a lookup table to allow the apc set point to change as a function of temperature to com- pensate for tracking error (te). the te lut (table 05h), has 36 entries that determine the apc setting in 4 c windows between -40 c to +100 c. ranging of the apc dac is possible by programming a single byte in table 02h. typical operating circuit ben+ ben- dis max3643 in- in+ out- bias- bias+ mdin compact burst mode laser driver DS1863 burst mode monitor/control circuit mdout out+ v cc tx-f tx-d scl sda mon2 mon3 fetg mon1 bmd 3.3v vmset modset vref imax gnd biasset benout mod bias ben biasmon vbest transmit power receive power i 2 c communication fault output disable input
DS1863 burst-mode pon controller with integrated monitoring _____________________________________________________________________ 9 modulation control the mod voltage is controlled using an internal tem- perature indexed lookup table. the mod output is an 8-bit scaleable voltage output that interfaces with the max3643 s vmset input. an external resistor to ground from the max3643 s modset pin sets the maximum current the voltage at vmset input can produce for a given output range. this resistor value should be chosen to produce the maximum modulation current the laser type requires over temperature. the modulation lut can be programmed in 2 c increments over the -40 c to +102 c range to provide temperature compensation for the laser s modulation. the modulation dac s scaling can be used (with apc scaling) to imple- ment gpon power leveling with a single lut that works for all three power levels. ranging of the mod dac is possible by programming a single byte in table 02h. bias and mod output during initial power-up on power-up the modulation and bias outputs will remain off until v cc is above v poa , a temperature con- version has been completed, and if the v cc lo adc alarm is enabled, then a v cc conversion above the customer defined v cc low alarm level has cleared the v cc low alarm. once all of these conditions are satis- fied, the mod output will be enabled with the value determined by the temperature conversion and the modulation lut. when the mod output is enabled and ben is high, the i bias dac output will be turned on to a value equal to i step (see above). the start-up algorithm checks if this bias current causes a feedback voltage above the apc set-point, and if it does not it continues increasing the i bias by i step until the apc set-point is exceeded. when the apc set point is exceeded, the device will begin a binary search to quickly reach the bias current corresponding to the proper power level. after the bina- ry search is completed the apc integrator is enabled, and single lsb steps are taken to tightly control the average power. all quick-trip and adc alarm flags are masked until the binary search is completed. however, the bias max alarm is monitored during this time to prevent the bias output from exceeding bias max. during the bias cur- rent initialization, the bias current is not allowed to exceed max ibias. if this occurs during the i step sequence then the binary search routine is enabled. if max ibias is exceeded during the binary search, then the next smaller step is activated. i step or binary incre- ments that would cause i bias to exceed max ibias are not taken. many of the alarm sources are likely to trip 1 2 3 4 5 6 7 8 9 10 11 12 13 t init v poa binary search apc integrator on t search power-up timing mod voltage bias current v cc bias sample i step 4x i step 3x i step 2x i step figure 1. DS1863 power-up.
DS1863 burst-mode pon controller with integrated monitoring 10 ____________________________________________________________________ during start-up. masking the alarms until the completion of the binary search prevents false alarms. i step is programmed by the customer using the start- up step register. this value should be programmed to the maximum safe current increase that is allowable during start-up. if this value is programmed too low, the DS1863 will still operate, but it could take significantly longer for the algorithm to converge and hence to con- trol the average power. if a fault is detected, and tx-d is toggled to re-enable the outputs, the DS1863 will power up following a similar sequence to an initial power up. the only difference is that the DS1863 already has determined the present tem- perature, so the t init time is not required for the DS1863 to recall the apc and mod set points from eeprom. bias and mod output as a function of transmit disable (tx-d) if tx-d is asserted (logic 1) during operation, the out- puts will immediately turn off (t off ). when tx-d is deasserted (logic 0), the DS1863 will turn on the mod output with the value associated with the present tem- perature, and initialize the i bias using the same search algorithm as done at start-up. soft tx-d (lower memory, register 6eh) when asserted would allow a software control identical to the tx-d pin. apc/quick-trip shared comparator timing the DS1863 s input comparator is shared between the apc control loop and the three quick-trip alarms (htxp, ltxp and hbias). the comparator polls the alarms in a round-robin multiplexed sequence. six of every eight of the comparator readings will be used for apc loop bias current control. the other two updates will be used to check the htxp/ltxp (monitor diode voltage) and the hbias (mon1) signals against the internal apc and bias reference. the htxp/ltxp com- parison will check htxp if the last bias-update compar- ison was above the apc set-point, and ltxp if the last bias update comparison was below the apc set-point. the DS1863 has a programmable comparator sample time based on an internally generated clock to facilitate a wide variety of external filtering options suitable for burst mode transmitter data rates between 155mbits/s and 1250mbits/s. the rising edge of burst enable (ben) trig- gers the sample to occur, and the sample rate register determines the delay. the internal clock is asynchronous to ben, causing a 100ns uncertainty as to when the first sample will occur following ben. after the first sample occurs, subsequent samples will occur on a regular interval. the following sample rate options are available. comparisons of the htxp, ltxp, and hbias quick-trip alarms will not occur during the burst enable low time. any quick-trip alarm that is detected will by default remain active until a subsequent comparator sample shows the condition no longer exists. a second bias current monitor compares the DS1863 s bias current dac s code to a digital value stored in the max ibias register. this comparison is made every bias current update to ensure that a high bias current will be quickly detected. tx-d timing (normal operation) tx-d i bias i mod t off t on t on t off figure 2. tx-d timing (output disabled during normal operating conditions). sr 3 sr 0 minimum time from ben to first sample (t first ) 50ns repeated sample period following first sample (t rep ) 0000b 350ns 800ns 0001b 550ns 1200ns 0010b 750ns 1600ns 0011b 950ns 2000ns 0100b 1350ns 2800ns 0101b 1550ns 3200ns 0110b 1750ns 3600ns 0111b 2150ns 4400ns 1000b 2950ns 6000ns 1001b* 3150ns 6400ns * all codes greater than 1001b (1010b?11b) use the maximum sample time of code 1001b.
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 11 monitors and fault detection monitors monitoring functions on the DS1863 include four quick- trip comparators and five adc channels this monitoring combined with the interrupt masks determines when/if the DS1863 shuts down its outputs and triggers the tx-f and fetg outputs. all of the mon- itoring levels and interrupt masks are user programma- ble with the exception of poa, which trips at a fixed range and is non-maskable for safety reasons. four quick-trip monitors and alarms four quick-trip monitors are provided to detect potential laser safety issues. these monitor 1) high bias current (hbias) 2) low transmit power (ltxp) 3) high transmit power (htxp) 4) max output current (max ibias) the high and low transmit power quick-trip registers (htxp and ltxp) set the thresholds used to compare against the bmd voltage to determine if the transmit power is within specification. the hbias quick-trip compares the mon1 input (generally from the max3643 bias monitor output) against its threshold set- ting to determine if the present bias current is above specification. the max bias quick-trip is a digital com- parison that determines if the bias output code indi- cates the bias current is above specification. the bias current will not be allowed to exceed the value set in this register. when the DS1863 detects the bias is at the limit it will set the bias max status bit and hold the bias current at the max ibias level. the quick-trips are routed to the tx-f and fetg outputs via interrupt masks to allow combinations of these alarms to be used to trigger these outputs. any time fetg is trig- gered the DS1863 will also disable its outputs. all the quick-trip alarm levels and masks are programmable through the i 2 c interface. five adc monitors and alarms the adc monitors five channels that measure tempera- ture (internal temp sensor), v cc , mon1, mon2, and mon3 using an analog multiplexer to measure them round robin with a single adc. each channel has a customer programmable full scale range and offset value that will be factory programmed to default value (see below). additionally, mon1, mon2, and mon3 have the ability to right shift results by up to 7 bits before the results are compared to alarm thresholds or read over the i 2 c bus. this allows customers with spec- ified adc ranges to calibrate the adc full scale to a factor of 1/2 n of their specified range to measure small signals. the DS1863 can then right shift the results by n bits to maintain the bit weight of their specification. the adc results (after right shifting, if used) are com- pared to high alarm thresholds (to check if the results exceeded this threshold), the low alarm thresholds (to check if the adc results are below this threshold) and the warning threshold after each conversion (20 com- parisons total), and the corresponding alarms are set which can be used to trigger the tx-f or fetg outputs. these adc thresholds are user programmable via the i 2 c interface, as are the masking registers that can be apc loop/quick trip sample timing last burst's bias sample ben bias dac code quick-trip sample times hbias sample t first t rep h/ltxp sample bias sample bias sample bias sample bias sample bias sample bias sample bias sample figure 3. apc/quick-trip alarm sample timing. adc default monitor full scale ranges signal (units) + fs signal + fs hex - fs signal - fs hex temperature ( o c) 127.996 7fff -128 8000 v cc (v) 6.5528 fff8 0v 0000 mon1, mon2, mon3 (v) 2.4997 fff8 0v 0000
DS1863 burst-mode pon controller with integrated monitoring 12 ____________________________________________________________________ used to prevent the alarms from triggering the tx-f and fetg outputs. see below for more detail on the tx-f and fetg outputs. adc timing there are five analog channels that are digitized in a round robin fashion in the order shown in figure 4. the total time required to convert all five channels is t rr (see electrical specifications for details). right shifting a/d conversion result if the weighting of the adc digital reading must con- form to a predetermined full-scale (pfs) value defined by a specification, then right shifting can be used to adjust the pfs analog measurement range while main- taining the weighting of the adc results. the DS1863 s range is wide enough to cover all requirements; when maximum input value is far short of the fs value, right shifting can be used to obtain greater accuracy. for instance, the maximum voltage might be 1/8 of the specified pfs value, so only 1/8 of the converter s range is effective over this range. an alternative is to calibrate the adc s full scale range to 1/8 the readable pfs value and use a right-shift value of 3. with this implementation, the resolution of the measurement has increased by a factor of 8, and because the result is digitally divided by 8 by right shifting, the bit weight of the measurement still meets the standard. the right shift operation on the a/d converter results is carried out based on the contents of right shift control registers (table 02h registers 8eh to 8fh) in eeprom. three analog channels: mon1 to mon3 each have 3 bits allocated to set the number of right shifts. up to 7 right shift operations are allowed and will be executed as a part of every conversion before the results are compared to the high and low alarm levels, or loaded into their corresponding measurement registers 62h to 69h. this is true during the setup of internal calibration as well as during subsequent data conversions. transmit fault (tx-f) output the tx-f output has masking registers for the five adc alarms and the four qt alarms to select which compar- isons cause it to assert. in addition, the fetg alarm is selectable via the tx-f mask to cause tx-f to assert. all alarms, with the exception of fetg, will only cause tx-f to remain active while the alarm condition persists. however, the tx-f latch bit can enable the tx-f output to remain active until it is cleared by the tx-f reset bit, tx-d, soft tx-d, or by power cycling the part. if the fetg output is configured to trigger tx-f, then it is indi- cating that the DS1863 is in shutdown, and will require tx-d, soft tx-d, or cycling power to reset. the adc and quick-trip alarms (with the exception of bias max) are ignored for the first 8-10 bias current updates dur- ing power up. only enabled alarms will activate tx-f. the following table shows tx-f as a function of tx-d and the alarm sources. safety shutdown (fetg) output the fetg output has masking registers (separate from tx-f) for the five adc alarms and the four qt alarms to select which comparisons cause it to assert. unlike tx-f, normal adc sample timing temp vcc mon1 mon2 mon3 temp vcc one round-robin adc cycle mon3 t rr figure 4. adc round-robin timing. if v cc low alarm is set for either the tx-f or fetg output, the round robin timing will cycle between only temp and v cc . tx-f as a function of tx-d and alarm sources v cc > v poa tx-d non-masked tx-f alarm tx-f no x x 1 yes 0 0 0 yes 0 1 1 yes 1 x 0
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 13 fetg output is always latched in case it is triggered by an unmasked alarm condition. its output polarity is pro- grammable to allow an external n or p mosfet to open during alarms to shut off the laser diode current. if the fetg output triggers indicating the DS1863 is in shut- down, then it requires tx-d, soft tx-d, or cycling power to be reset. under all conditions when the analog outputs are re-initialized after being disabled, all the alarms with the exception of the v cc low adc alarm will be cleared. the v cc low alarm must remain active to prevent the out- put from attempting to operate when inadequate v cc exists to operate the laser driver. once adequate v cc is present to clear the v cc low alarm, the outputs will be enabled following the same sequence as power up. as mentioned before the fetg is an output used to dis- able the laser current via a series n or p mosfet. this requires that the fetg output is capable of sinking or sourcing current. because the DS1863 will not know if it should sink or source current before v cc exceeds v poa , which triggers the ee recall, this output will be high impedance when v cc is below v poa . (see low voltage operation section for details and diagram). the application circuit must use a pull-up or pull-down resistor on this pin that pulls fetg to the alarm/shut- down state (high for a pmos, low for a nmos). once v cc is above v poa , the DS1863 will pull the fetg out- put to the state determined by the fetg dir bit (table 02h, register 89h). fetg dir will be 0 if an nmos is used and 1 is a pmos is used. determining alarm causes using the i 2 c interface to determine the cause of the tx-f or fetg alarm, the system processor can read the DS1863 s alarm trap bytes (atb) through the i 2 c interface (in table 01h). the atb have a bit for each alarm. any time an alarm occurs, regardless of the mask bit s state, the DS1863 sets the corresponding bit in the atb. active atb bits will remain set until written to zeros via the i 2 c interface. on power up the atb will be zeros until alarms dictate otherwise. die identification DS1863 will have an id hard coded to its die. two reg- isters (table 02h bytes 86h 87h) are assigned for this feature. byte 86h will read 63h to identify the part as the DS1863, byte 87h will read to a1h (for a1 die revision). low-voltage operation the DS1863 contains two power-on reset (por) lev- els. the lower level is a digital por (v pod ) and the tx-f latched operation tx-f non-latched operation detection of tx-f fault tx-d or tx-f reset tx-f detection of tx-f fault tx-f figure 5. DS1863 tx-f timing. fetg and mod and bias outputs as a function of tx-d and alarm sources v cc > v poa tx-d non-masked fetg alarm fetg mod and bias outputs yes 0 0 fetg dir enabled yes 0 1 fetg dir disabled yes 1 x fetg dir disabled
DS1863 burst-mode pon controller with integrated monitoring 14 ____________________________________________________________________ higher level is an analog por (v poa ). at start up, before the supply voltage rises above v poa , the out- puts are disabled (fetg and bias outputs are high impedance, mod is low), all sram outputs are low (including shadowed eeprom), and all analog circuit- ry is disabled. when v cc reaches v poa , the see is recalled, and the analog circuitry is enabled. while v cc remains above v poa , the device is in its normal operating state, and it responds based on its non- volatile configuration. if during operation v cc falls below v poa , but is still above v pod , then the sram will retain the see settings from the first see recall, but the device analog will be shut down and the outputs disabled. fetg will be driven to its alarm state defined by the fetg dir bit (table 02h, register 89h). if the supply voltage recovers back above v poa , then the device will immediately resume normal functioning. if the supply voltage falls below v pod , then the device sram will be placed in its default state and another see recall will be required to reload the nonvolatile set- tings. the eeprom recall will occur the next time v cc next exceeds v poa . figure 7 shows the sequence of events as the voltage varies. any time v cc is above v pod , the i 2 c interface can be used to determine if v cc is below the v poa level. this is accomplished by checking the rdyb bit in the status (6eh) byte. rdyb is set when v cc is below v poa ; when v cc rises above v poa rdyb is timed (within 500s) to go to 0, at which point the part is fully functional. for all device addresses sourced from eeprom (byte 8ch, table 01h in memory) the default device address is a2h until v cc exceeds v poa allowing the device address to be recalled from the eeprom. power-on analog (poa) poa holds the DS1863 in reset until v cc is at a suitable level (v cc > v poa ) for the part to accurately measure with its adc and compare analog signals with its quick- trip monitors. because v cc cannot be measured by the adc when v cc is less than v poa , poa also asserts the v cc low alarm, which must be cleared by a v cc adc conversion that is greater than the customer programma- ble v cc low adc limit. this prevents the tx-f and fetg outputs from glitching during a slow power up. the tx-f and fetg output will not latch until there is a conversion above v cc low limit. the poa alarm is non-maskable. the tx-f, and fetg outputs shuts off any time v cc is below v poa . see low voltage operation section for more information. fetg/output disable timing (fault condition detected) i bias i mod detection of fetg fault t off t on t on t off tx-d t fetg:on fetg t fetg:off figure 6. fetg/modulation and bias timing (fault condition detected).
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 15 DS1863 memory map memory organization the DS1863 features six memory banks that include the following. the lower memory is addressed from 00h to 7fh and contains alarm and warning thresholds, flags, masks, several control registers, password entry area (pwe), and the table select byte. the table select byte deter- mines which table (01h 05h) will be mapped into the upper memory locations. table 01h primarily contains user eeprom (with pw1 level access) as well as some alarm and warning sta- tus bytes. table 02h is a multifunction space that contains configuration registers, scaling and offset values, passwords, interrupt registers as well as other miscella- neous control bytes. table 03h is strictly user eeprom that is protected by a pw2 level password. table 04h contains a temperature indexed look up table (lut) for control of the modulation voltage. the modulation lut can be programmed in 2 c increments over the -40 c to +102 c range. access to this register is protected by a pw2 level password. table 05h contains another lut which allows the apc set point to change as a function of temperature to compensate for tracking error (te). this te lut, has 36 entries that determine the apc setting in 4 c win- dows between -40 c to 100 c. access to this register is protected by a pw2 level password. complete detail of each byte s function, as well as read/write permissions for each byte for each table is provided in the register descriptions sections. shadowed eeprom many nonvolatile (nv) memory locations (listed within the detailed register description section) are actually shadowed-eeprom which are controlled by the seeb bit in table 02h, byte 80h. the DS1863 incorporates shadowed eeprom memory locations for key memory addresses that may be re- written many times. by default the shadowed eeprom bit, seeb, is not set and these locations act as ordinary eeprom. by setting seeb these locations function like sram cells, which allow an infinite number of write cycles without concern of wearing out the eeprom. this also eliminates the requirement for the eeprom write time, t wr . because changes made with seeb enabled do not affect the eeprom, these changes are not retained through power cycles. the power-up value is the last value written with seeb disabled. this func- tion can be used to limit the number of eeprom writes during calibration or to change the monitor thresholds periodically during normal operation helping to reduce the number of times eeprom is written. the memory map description indicates which locations are shad- owed-eeprom. v cc v poa v pod fetg see* high impedance high impedance high impedance normal operation driven to fetg dir normal operation precharged to 0 precharged to 0 precharged to 0 recalled value recalled value driven to fetg dir normal operation driven to fetg dir see recall see recall figure 7. DS1863 digital and analog power-on reset.
DS1863 burst-mode pon controller with integrated monitoring 16 ____________________________________________________________________ i 2 c definitions master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses, start and stop conditions. slave devices: slave devices send and receive data at the master s request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and in their logic-high states. when the bus is idle it often initi- ates a low-power mode for slave devices. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see the timing dia- gram for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. see the timing dia- gram for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data trans- fer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a table select byte misc. control bits password entry (pwe) (4 bytes) digital diagnostic functions 7fh i 2 c slave address a2h 00h ffh 80h pw1 level access eeprom (120 bytes) table 01h lower memory ffh f7h 80h c0h configuration and control empty table 02h ffh 80h pw2 level access eeprom (128 bytes) table 03h c7h 80h modulation voltage control temperature indexed lut table 04h a7h 80h tracking error lut for temperature indexed control of apc set-point table 05h dec 0 hex 0 127 7f 128 80 248 f8 255 ff figure 8. DS1863 memory map.
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 17 specific memory address to begin a data transfer. a repeated start condition is issued identically to a nor- mal start condition. see the timing diagram for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold-time requirements (figure 9). data is shift- ed into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowledge- ment (ack) or not acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmit- ting a zero during the 9th bit. a device performs a nack by transmitting a one during the 9th bit. timing for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is prop- erly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of information transferred from the master to the slave (most signifi- cant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the mas- ter are done according to the bit write definition and the acknowledgement is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave will return control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave addressing byte (figure 10) sent immediately following a start condition. the slave address byte contains the slave address in the most sig- nificant 7 bits and the r/ w bit in the least significant bit. the DS1863 s slave address can be configured to any value between 00h to feh using the device address byte (table 02h, register 8ch). the user also has to set the asel bit (table 02h, register 89h) for this address to be active. the default address is a2h (see figure 10). by writing the correct slave address with r/ w = 0, the mas- ter indicates it will write data to the slave. if r/ w = 1, the master will read data from the slave. if an incorrect slave address is written, the DS1863 will assume the master is communicating with another i 2 c device and ignore the communications until the next start condition is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte trans- mitted during a write operation following the slave address byte. sda scl t hd:sta t low t high t r t f t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start t buf note: timing is referenced to v il(max) and v ih(min) . figure 9. i 2 c timing diagram.
DS1863 burst-mode pon controller with integrated monitoring 18 ____________________________________________________________________ i 2 c communication writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the byte of data, and generate a stop condition. the master must read the slave s acknowledgement during all byte write operations. writing multiple bytes to a slave: to write multiple bytes to a slave, the master generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address, writes up to 8 data bytes, and gener- ates a stop condition. the DS1863 writes 1 to 8 bytes (1 page or row) with a single write transaction. this is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. the address counter limits the write to one 8-byte page (one row of the memory map). attempts to write to additional pages of memory without sending a stop condition between pages results in the address counter wrapping around to the beginning of the present row. example: a 3-byte write starts at address 06h and writes three data bytes (11h, 22h, and 33h) to three consecutive addresses. the result is that addresses 06h and 07h would contain 11h and 22h, respectively, and the third data byte, 33h, would be written to address 00h. to prevent address wrapping from occurring, the mas- ter must send a stop condition at the end of the page, then wait for the bus-free or eeprom-write time to elapse. then the master can generate a new start con- dition, and write the slave address byte (r/ w = 0) and the first memory address of the next memory row before continuing to write data. acknowledge polling: any time an eeprom location is written, the DS1863 requires the eeprom write time (t w ) after the stop condition to write the contents of the byte of data to eeprom. during the eeprom write time, the device will not acknowledge its slave address because it is busy. it is possible to take advantage of that phenomenon by repeatedly addressing the DS1863, which allows the next page to be written as soon as the DS1863 is ready to receive the data. the alternative to acknowledge polling is to wait for a maxi- mum period of t w to elapse before attempting to write again to the device. eeprom write cycles: when eeprom writes occur to the memory, the DS1863 will write to all three eeprom memory locations, even if only a single byte was modi- fied. because all three bytes are written, the bytes that were not modified during the write transaction are still subject to a write cycle. this can result in all three bytes being worn out over time by writing a single byte repeat- edly. the DS1863 s eeprom write cycles are specified in the nv memory characteristics table. the specification shown is at the worst-case temperature. if zero-crossing detection is enabled, eeprom write cycles cannot begin until after the zero-crossing detection is complete. reading a single byte from a slave: to read a single byte from the slave, the master generates a start con- dition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. when a single byte is read, it will always be the potentiometer 0 value. reading multiple bytes from a slave: the read oper- ation can be used to read multiple bytes with a single transfer. when reading bytes from the slave, the master simply acks the data byte if it desires to read another byte before terminating the transaction. after the mas- ter reads the last byte, it nacks to indicate the end of the transfer and generates a stop condition. the first byte read will be the potentiometer 0 wiper setting. the next byte will be the potentiometer 1 wiper setting. the third byte is the configuration register byte. if an ack is issued by the master following the configuration register byte, then the DS1863 will send the potentiometer 0 wiper setting again. this round robin reading will occur as long as each byte read is followed by an ack from the master. the default slave address is shown, however it can be changed using the device address byte (table 02h, byte 8ch)., and asel bit. 1 msb slave address* lsb 010001 r/w read/write bit figure 10. DS1863 slave address byte (default)
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 19 lower memory word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 00 <1> threshold 0 temp alarm hi temp alarm lo temp warn hi temp warn lo 08 <1> threshold 1 v cc alarm hi v cc alarm lo v cc warn hi v cc warn lo 10 <1> threshold 2 mon1 alarm hi mon1 alarm lo mon1 warn hi mon1 warn lo 18 <1> threshold 3 mon2 alarm hi mon2 alarm lo mon2 warn hi mon2 warn lo 20 <1> threshold 4 mon3 alarm hi mon3 alarm lo mon3 warn hi mon3 warn lo 28 <1> shadowed ee see see see see see see see see 30 <1> pw2 ee ee ee ee ee ee ee ee ee 38 <1> pw2 ee ee ee ee ee ee ee ee ee 40 <1> pw2 ee ee ee ee ee ee ee ee ee 48 <1> pw2 ee ee ee ee ee ee ee ee ee 50 <1> pw2 ee ee ee ee ee ee ee ee ee 58 <1> pw2 ee ee ee ee ee ee ee ee ee 60 <2> adc values 0 temp value v cc value mon1 value mon2 value 68 <0> adc values 1 <2> mon3 value <2> reserved <2> reserved <0> status <3> update 70 <2> alarm/warn alarm 3 alarm 2 alarm 1 alarm 0 warn 3 warn 2 reserved 78 <0> table select <6> reserved <6> reserved <6> reserved <6> pwe msb <6> pwe lsb <5> tbl sel access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access s ee each b i t /b yt e s ep ar at el y pw2 n/a al l and DS1863 har dwar e pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 lower memory register map this register map shows each byte/word in terms of the row it is on in the memory. the first byte in the row is located in memory at the row address (hexadecimal) in the left most column. each subsequent byte on the row is one/ two memory locations beyond the previous byte/word s address. a total of eight bytes are present on each row. for more information about each of these bytes see the corresponding register description.
DS1863 burst-mode pon controller with integrated monitoring 20 ____________________________________________________________________ table 01h. register map table 01h (pw1) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <7> pw1 ee ee ee ee ee ee ee ee ee 88 <7> pw1 ee ee ee ee ee ee ee ee ee 90 <7> pw1 ee ee ee ee ee ee ee ee ee 98 <7> pw1 ee ee ee ee ee ee ee ee ee a0 <7> pw1 ee ee ee ee ee ee ee ee ee a8 <7> pw1 ee ee ee ee ee ee ee ee ee b0 <7> pw1 ee ee ee ee ee ee ee ee ee b8 <7> pw1 ee ee ee ee ee ee ee ee ee c0 <7> pw1 ee ee ee ee ee ee ee ee ee c8 <7> pw1 ee ee ee ee ee ee ee ee ee d0 <7> pw1 ee ee ee ee ee ee ee ee ee d8 <7> pw1 ee ee ee ee ee ee ee ee ee e0 <7> pw1 ee ee ee ee ee ee ee ee ee e8 <7> pw1 ee ee ee ee ee ee ee ee ee f0 <7> pw1 ee ee ee ee ee ee ee ee ee f8 <11> alarm trap alarm 3 alarm 2 alarm 1 alarm 0 warn 3 warn 2 reserved access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access s ee each b i t /b yt e s ep ar at el y pw2 n/a al l and DS1863 har dwar e pw2 + mode bit all all pw1 pw2 pw2 n/a pw1
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 21 table 02h. register map table 02h (pw2) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <0> config 0 <8> mode <4> tindex <4> mod dac <4> apc dac < 4> bias dac 2 < 4> bias dac 2 < 10 > dev ice id <10> device ver 88 <8> config 1 update rate config start-up step mod ranging device address comp ranging rshift 1 rshift 0 90 <8> scale 0 reserved v cc scale mon1 scale mon2 scale 98 <8> scale 1 mon3 scale reserved reserved reserved a0 <8> offset 0 reserved v cc offset mon1 offset mon2 offset a8 <8> offset 1 mon3 offset reserved reserved internal temp offset* b0 < 9> p wd v alu e pw1 msb pw1 lsb pw2 msb pw2 lsb b8 <8> interrupt fetg en 1 fetg en 0 tx-f en 1 tx-f en 0 htxp ltxp hbias max ibias c0-f7 empty empty empty empty empty empty empty empty empty f8 <4> man ibias man ibias 0 man ibias 1 man_cntl reserved reserved reserved reserved reserved access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access s ee each b i t /b yt e s ep ar at el y pw2 n/a al l and DS1863 har dwar e pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 * the final result must be xor?d with bb40h before writing to this register.
DS1863 burst-mode pon controller with integrated monitoring 22 ____________________________________________________________________ table 03h. register map table 03h (pw2) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <8> pw2 ee ee ee ee ee ee ee ee ee 88 <8> pw2 ee ee ee ee ee ee ee ee ee 90 <8> pw2 ee ee ee ee ee ee ee ee ee 98 <8> pw2 ee ee ee ee ee ee ee ee ee a0 <8> pw2 ee ee ee ee ee ee ee ee ee a8 <8> pw2 ee ee ee ee ee ee ee ee ee b0 <8> pw2 ee ee ee ee ee ee ee ee ee b8 <8> pw2 ee ee ee ee ee ee ee ee ee c0 <8> pw2 ee ee ee ee ee ee ee ee ee c8 <8> pw2 ee ee ee ee ee ee ee ee ee d0 <8> pw2 ee ee ee ee ee ee ee ee ee d8 <8> pw2 ee ee ee ee ee ee ee ee ee e0 <8> pw2 ee ee ee ee ee ee ee ee ee e8 <8> pw2 ee ee ee ee ee ee ee ee ee f0 <8> pw2 ee ee ee ee ee ee ee ee ee f8 <8> pw2 ee ee ee ee ee ee ee ee ee access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access s ee each b i t /b yt e s ep ar at el y pw2 n/a al l and DS1863 har dwar e pw2 + mode bit all all pw1 pw2 pw2 n/a pw1
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 23 table 04h. register map table 04h (lut for mod) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <8> lut4 mod mod mod mod mod mod mod mod 88 <8> lut4 mod mod mod mod mod mod mod mod 90 <8> lut4 mod mod mod mod mod mod mod mod 98 <8> lut4 mod mod mod mod mod mod mod mod a0 <8> lut4 mod mod mod mod mod mod mod mod a8 <8> lut4 mod mod mod mod mod mod mod mod b0 <8> lut4 mod mod mod mod mod mod mod mod b8 <8> lut4 mod mod mod mod mod mod mod mod c0 <8> lut4 mod mod mod mod mod mod mod mod table 05h. register map table 05h (lut for apc) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <8> lut5 apc ref apc ref apc ref apc ref apc ref apc ref apc ref apc ref 88 <8> lut5 apc ref apc ref apc ref apc ref apc ref apc ref apc ref apc ref 90 <8> lut5 apc ref apc ref apc ref apc ref apc ref apc ref apc ref apc ref 98 <8> lut5 apc ref apc ref apc ref apc ref apc ref apc ref apc ref apc ref a0 <8> lut5 apc ref apc ref apc ref apc ref re se rv ed re se rv ed re se rv ed re se rv ed access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access s ee each b i t /b yt e s ep ar at el y pw2 n/a al l and DS1863 har dwar e pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 springer
DS1863 burst-mode pon controller with integrated monitoring 24 ____________________________________________________________________ lower memory register 00h to 01h: temp alarm hi factory default: 7fffh read access all write access pw2 memory type: nonvolatile (see) 00h s2 6 2 5 2 4 2 3 2 2 2 1 2 0 01h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit7 bit0 temperature measurements above this 2? complement threshold will set its corresponding alarm bit. measurements equal to or below this threshold will clear its alarm bit. lower memory register 02h to 03h: temp alarm lo factory default: 8000h read access all write access pw2 memory type: nonvolatile (see) 02h s2 6 2 5 2 4 2 3 2 2 2 1 2 0 03h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit7 bit0 temperature measurements above this 2 s complement threshold will set its corresponding alarm bit. measurements equal to or below this threshold will clear its alarm bit. lower memory register 04h to 05h: temp warn hi factory default: 7fffh read access all write access pw2 memory type: nonvolatile (see) 04h s2 6 2 5 2 4 2 3 2 2 2 1 2 0 05h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit7 bit0 temperature measurements above this 2 s complement threshold will set its corresponding warning bit. measurements equal to or below this threshold will clear its warning bit. lower memory registers description
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 25 lower memory register 06h to 07h: temp warn lo factory default: 8000h read access all write access pw2 memory type: nonvolatile (see) 06h s2 6 2 5 2 4 2 3 2 2 2 1 2 0 07h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit7 bit0 temperature measurements below this 2 s complement threshold will set its corresponding warning bit. measurements above this threshold will clear its warning bit. lower memory register 08h to 09h: v cc alarm hi factory default: ffffh read access all write access pw2 memory type: nonvolatile (see) 08h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 09h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 voltage measurements of the v cc input above this unsigned threshold will set its corresponding alarm bit. measurements below this threshold will clear its alarm bit. lower memory register 0ah to 0bh: v cc alarm lo factory default: 0000h read access all write access pw2 memory type: nonvolatile (see) 0ah 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 0bh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 voltage measurements of the v cc below above this unsigned threshold will set its corresponding alarm bit. measurements above this threshold will clear its alarm bit.
DS1863 burst-mode pon controller with integrated monitoring 26 ____________________________________________________________________ lower memory register 0eh to 0fh: v cc warn lo factory default: 0000h read access all write access pw2 memory type: nonvolatile (see) 0eh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 0fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 v ol tag e m easur em ents of the v c c b el ow ab ove thi s unsi g ned thr eshol d w i l l set i ts cor r esp ond i ng w ar ni ng b i t. m easur em ents ab ove thi s thr eshol d w i l l cl ear i ts w ar ni ng b i t. lower memory register 10h to 11h: mon1 alarm hi factory default: ffffh read access all write access pw2 memory type: nonvolatile (see) 10h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 11h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 voltage measurements of the mon1 input above this unsigned threshold will set its corresponding alarm bit. measurements below this threshold will clear its alarm bit. lower memory register 0ch to 0dh: v cc alarm hi factory default: ffffh read access all write access pw2 memory type: nonvolatile (see) 0ch 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 0dh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 voltage measurements of the v cc input above this unsigned threshold will set its corresponding warning bit. measurements below this threshold will clear its warning bit.
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 27 lower memory register 12h to 13h: mon1 alarm lo factory default: 0000h read access all write access pw2 memory type: nonvolatile (see) 12h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 13h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 voltage measurements of the mon1 input below this unsigned threshold will set its corresponding alarm bit. measurements above this threshold will clear its alarm bit. lower memory register 14h to 15h: mon1 warn hi factory default: ffffh read access all write access pw2 memory type: nonvolatile (see) 14h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 15h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 voltage measurements of the mon1 input above this unsigned threshold will set its corresponding warning bit. measurements below this threshold will clear its warning bit. lower memory register 16h to 17h: mon1 warn lo factory default: 0000h read access all write access pw2 memory type: nonvolatile (see) 16h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 17h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 voltage measurements of the mon1 input below this unsigned threshold will set its corresponding warning bit. measurements above this threshold will clear its warning bit.
DS1863 burst-mode pon controller with integrated monitoring 28 ____________________________________________________________________ lower memory register 18h to 19h: mon2 alarm hi factory default: ffffh read access all write access pw2 memory type: nonvolatile (see) 18h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 19h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 voltage measurements of the mon2 input above this unsigned threshold will set its corresponding alarm bit. measurements below this threshold will clear its alarm bit. lower memory register 1ah to 1bh: mon2 alarm lo factory default: 0000h read access all write access pw2 memory type: nonvolatile (see) 1ah 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 1bh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 voltage measurements of the mon2 input below this unsigned threshold will set its corresponding alarm bit. measurements above this threshold will clear its alarm bit. lower memory register 1ch to 1dh: mon2 alarm hi factory default: ffffh read access all write access pw2 memory type: nonvolatile (see) 1ch 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 1dh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 voltage measurements of the mon2 input above this unsigned threshold will set its corresponding warning bit. measurements below this threshold will clear its warning bit.
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 29 lower memory register 1eh to 1fh: mon2 warn lo factory default: 0000h read access all write access pw2 memory type: nonvolatile (see) 1eh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 1fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 voltage measurements of the mon2 input below this unsigned threshold will set its corresponding warning bit. measurements above this threshold will clear its warning bit. lower memory register 20h to 21h: mon3 alarm hi factory default: ffffh read access all write access pw2 memory type: nonvolatile (see) 20h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 21h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 voltage measurements of the mon3 input above this unsigned threshold will set its corresponding alarm bit. measurements below this threshold will clear its alarm bit. lower memory register 22h to 23h: mon3 alarm lo factory default: 0000h read access all write access pw2 memory type: nonvolatile (see) 22h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 23h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 voltage measurements of the mon3 input below this unsigned threshold will set its corresponding alarm bit. measurements above this threshold will clear its alarm bit.
DS1863 burst-mode pon controller with integrated monitoring 30 ____________________________________________________________________ lower memory register 24h to 25h: mon3 warn hi factory default: ffffh read access all write access pw2 memory type: nonvolatile (see) 24h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 25h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 voltage measurements of the mon3 input above this unsigned threshold will set its corresponding warning bit. measurements below this threshold will clear its warning bit. lower memory register 26h to 27h: mon3 warn lo factory default: 0000h read access all write access pw2 memory type: nonvolatile (see) 26h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 27h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 voltage measurements of the mon3 input below this unsigned threshold will set its corresponding warning bit. measurements above this threshold will clear its warning bit. lower memory register 28h to 2fh: shadowed eeprom factory default: 00h read access all write access pw2 memory type: nonvolatile (see) 28h-2fh see see see see see see see see bit7 bit0 shadowed eeprom memory (see details in memory map section). pw2 level access controlled rom data for end user.
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 31 lower memory register 30h to 5fh: pw2 ee factory default: 00h read access all write access pw2 memory type: nonvolatile (ee) 30h-5fh ee ee ee ee ee ee ee ee bit7 bit0 nonvolatile eeprom memory. pw2 level access controlled rom data for end user. lower memory register 60h to 61h: temp value power-on value 0000h read access all write access n/a memory type: volatile 60h s2 6 2 5 2 4 2 3 2 2 2 1 2 0 61h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit7 bit0 signed 2 s complement direct-to-temperature measurement. lower memory, register 62h?3h: v cc value lower memory, register 64h?5h: mon1 value lower memory, register 66h?7h: mon2 value lower memory, register 68h?9h: mon3 value power-on value 0000h read access all write access n/a memory type: volatile 62h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 63h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 64h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 65h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 66h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 67h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 68h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 69h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 unsigned voltage measurement.
DS1863 burst-mode pon controller with integrated monitoring 32 ____________________________________________________________________ lower memory, register 6ah to 6d: reserved power-on value 00h read access all write access n/a memory type these registers are reserved. the value when read is 00h. lower memory, register 6eh: status power-on value x000 0x0x b read access all write access see below memory type volatile write access n/a all n/a all all n/a n/a n/a 6eh fetg status soft fetg reserved tx-f reset soft tx-d tx-f status reserved rdyb bit7 bit0 bit7 fetg status: reflects the active state of fetg. 0 = bias and modulation outputs are enabled. 1 = the fetg output is asserted to disable the bias and modulation outputs. bit6 soft fetg: 0 = (default) 1 = force the bias and modulation outputs to their off states and asserts the fetg output. bit5 reserved (default = 0) bit4 tx-f reset: 0 = does not affect the tx-f output (default). 1 = resets the latch for the tx-f output. this bit is self clearing after the reset. bit3 soft tx-d: this bit allows a software control that is identical to the tx-d pin. please see section on tx-d for further information. it s value is wired or ed with the logic value on tx-d pin. 0 = internal tx-d signal is equal to external tx-d pin. 1 = internal tx-d signal is high. bit2 tx-f status: reflects the active state of tx-f. 0 = tx-f pin is not active. 1 = tx-f pin is active. bit1 reserved (default = 0) bit0 rdyb: ready bar. 0 = v cc is above poa. 1 = v cc is below poa or too low to communicate over the i 2 c bus.
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 33 lower memory, register 6fh: update power-on value 00h read access all write access all + DS1863 hardware memory type volatile 6fh temp rdy v cc rdy mon1 rdy mon2 rdy mon3 rdy reserved reserved reserved bit7 bit0 status of completed conversions. at power-on, these bits are cleared and will be set as each conversion is completed. these bit s can be cleared so that a completion of a new conversion is verified. bit7 temp rdy: 0 = temperature conversion is not ready (default). 1 = temperature conversion is ready. bit6 v cc rdy: 0 = v cc conversion is not ready (default). 1 = v cc conversion is ready. bit5 mon1 rdy: 0 = mon1 conversion is not ready (default). 1 = mon1 conversion is ready. bit4 mon2 rdy: 0 = mon2 conversion is not ready (default). 1 = mon2 conversion is ready. bit3 mon3 rdy: 0 = mon3 conversion is not ready (default). 1 = mon3 conversion is ready. bit2:0 reserved
DS1863 burst-mode pon controller with integrated monitoring 34 ____________________________________________________________________ lower memory, register 70h: alarm 3 power-on value 10h read access all write access n/a memory type volatile 70h temp hi temp lo v cc hi v cc lo mon1 hi mon1 lo mon2 hi mon2 lo bit7 bit0 alarm status bits bit7 temp hi: high alarm status for temperature measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit6 temp lo: low alarm status for temperature measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit5 v cc hi: high alarm status for v cc measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit4 v cc lo: low alarm status for v cc measurement. this bit is set when the v cc supply is below the poa trip point value. it will clear itself when a v cc measurement is completed and the value is above the low threshold. 0 = last measurement was equal to or above threshold setting. 1 = (default) last measurement was below threshold setting. bit3 mon1 hi: high alarm status for mon1 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit2 mon1 lo: low alarm status for mon1 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit1 mon2 hi: high alarm status for mon2 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit0 mon2 lo: low alarm status for mon2 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting.
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 35 lower memory, register 71h: alarm 2 power-on value 00h read access all write access n/a memory type volatile 71h mon3 hi mon3 lo reserved reserved reserved reserved reserved reserved bit7 bit0 alarm status bits bit7 mon3 hi: high alarm status for mon3 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit6 mon3 lo: low alarm status for mon3 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit5:0 reserved
DS1863 burst-mode pon controller with integrated monitoring 36 ____________________________________________________________________ lower memory, register 72h: alarm 1 power-on value 00h read access all write access n/a memory type volatile 72h reserved reserved reserved reserved bias hi reserved tx-p hi tx-p lo bit7 bit0 alarm status bits bit7:4 reserved bit3 bias hi: high alarm status bias; fast comparison. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit2 reserved bit1 tx-p hi: high alarm status tx-p; fast comparison. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit0 tx-p lo: low alarm status tx-p; fast comparison. 0 = last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. lower memory, register 73h: alarm 0 power-on value 00h read access all write access n/a memory type volatile 73h reserved reserved reserved reserved bias max reserved reserved reserved bit7 bit0 alarm status bits bit7:4 reserved bit3 bias max: maximum digital setting for ibias. 0 = (default) the value of ibias is equal to or below max ibias setting. 1 = requested value of ibias is greater than max ibias setting. bit2:0 reserved
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 37 lower memory, register 74h: warn 3 power-on value 10h read access all write access n/a memory type volatile 74h temp hi temp lo v cc hi v cc lo mon1 hi mon1 lo mon2 hi mon2 lo bit7 bit0 warning status bits bit7 temp hi: high warning status for temperature measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit6 temp lo: low warning status for temperature measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit5 v cc hi: high warning status for v cc measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit4 v cc lo: low warning status for v cc measurement. this bit is set when the v cc supply is below the poa trip point value. it will clear itself when a v cc measurement is completed and the value is above the low threshold. 0 = last measurement was equal to or above threshold setting. 1 = (default) last measurement was below threshold setting. bit3 mon1 hi: high warning status for mon1 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit2 mon1 lo: low warning status for mon1 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit1 mon2 hi: high warning status for mon2 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit0 mon2 lo: low warning status for mon2 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting.
DS1863 burst-mode pon controller with integrated monitoring 38 ____________________________________________________________________ lower memory, register 75h: warn 2 power-on value 10h read access all write access n/a memory type volatile 75h mon3 hi mon3 lo reserved reserved reserved reserved reserved reserved bit7 bit0 warning status bits bit7 mon3 hi: high warning status for mon3 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit6 mon3 lo: low warning status for mon3 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit5 reserved lower memory, register 76h to 7ah: reserved power-on value 00h read access all write access n/a memory type these registers are reserved. the value when read is 00h. lower memory, register 7bh to 7eh: password entry (pwe) factory default ffff ffffh read access n/a write access all memory type volatile 7bh 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 7ch 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 7dh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 7eh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 password entry. there are two passwords for the DS1863. each password is 4 bytes long. the lower level password (pw1) will have all the access of a normal user plus those made available with pw1. the higher level password (pw2) will have all of the access of pw1 plus those made available with pw2. the values of the passwords reside in ee inside of pw2 memory. at power up all pwe bits are set to 1. all reads to this location are 0.
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 39 lower memory register 7fh: table select (tbl sel) power-on value 00h read access all write access all memory type volatile 7fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the upper memory tables (table 01h table 05h) of the DS1863 are accessible by writing the correct table value in this register.
DS1863 burst-mode pon controller with integrated monitoring 40 ____________________________________________________________________ table 01h, register f8h: alarm 3 power-on value 00h read access all write access pw1 memory type volatile f8h temp hi temp lo v cc hi v cc lo mon1 hi mon1 lo mon2 hi mon2 lo bit7 bit0 layout is identical to alarm 3 in lower memory register 70h with two exceptions. 1. v cc low alarm is not set at power-on. 2. these bits are latched. they are cleared by power-down or a write with pw1 access. table 01h, register 80h to f7h: pw1 eeprom power-on value 00h read access pw1 write access pw1 memory type nonvolatile(ee) 80h-f7h ee ee ee ee ee ee ee ee bit7 bit0 eeprom for pw1 level access. table 01h, registers table 01h, register f9h: alarm 2 power-on value 00h read access all write access pw1 memory type volatile f9h mon3 hi mon3 lo reserved reserved reserved reserved reserved reserved bit7 bit0 layout is identical to alarm 2 in lower memory register 71h with one exception. 1. these bits are latched. they are cleared by power-down or a write with pw1 access.
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 41 table 01h, register fbh: alarm 0 power-on value 00h read access all write access pw1 memory type volatile 72h reserved reserved reserved reserved bias max reserved reserved reserved bit7 bit0 layout is identical to alarm 0 in lower memory register 73h with one exception. 1. these bits are latched. they are cleared by power-down or a write with pw1 access table 01h, register fah: alarm 1 power-on value 00h read access all write access pw1 memory type volatile fah bias hi tx-p hi tx-p lo reserved reserved reserved reserved reserved bit7 bit0 layout is identical to alarm 1 in lower memory register 72h with one exception. 1. these bits are latched. they are cleared by power-down or a write with pw1 access. table 01h, register fch: warn 3 power-on value 00h read access all write access pw1 memory type volatile fch temp hi temp lo v cc hi v cc lo mon1 hi mon1 lo mon2 hi mon2 lo bit7 bit0 layout is identical to warn 3 in lower memory register 74h with two exceptions. 1. v cc low warning is not set at power-on. 2. these bits are latched. they are cleared by power-down or a write with pw1 access.
DS1863 burst-mode pon controller with integrated monitoring 42 ____________________________________________________________________ table 01h, register fdh: warn 2 power-on value 00h read access all write access pw1 memory type volatile fdh mon3 hi mon3 lo reserved reserved reserved reserved reserved reserved bit7 bit0 layout is identical to warn 2 in lower memory register 75h with one exception. 1. these bits are latched. they are cleared by power-down or a write with pw1 access. table 01h, register feh to ffh: reserved power-on value 00h read access all write access pw1 memory type volatile these registers are reserved.
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 43 table 02h, register 80h: mode power-on value 0fh read access pw2 write access pw2 memory type volatile 80h seeb reserved reserved reserved aen mod-en apc-en bias-en bit7 bit0 bit7 seeb: 0 = enables eeprom writes to see bytes in table 02h (default). 1 = disables eeprom writes to see bytes during configuration, so that the configuration of the part is not delayed by the ee cycle time. once the values are known, write this bit to a 0 and write the see locations again for data to be written to the eeprom. bit6:4 reserved bit3 aen: 0 = the temperature calculated index value ( t index ) is write-able by the user and the updates of calculated indexes are disabled. this allows the user to interactively test their modules by controlling the indexing for the look-up tables. the recalled values from the luts will appear in the dac registers after the next completion of a temperature conversion (just like it would happen is auto mode). both dacs will update at the same time (just like auto mode). 1 = enables auto control of the lut (default). bit2 mod-en: 0 = mod dac is write-able by the user and the lut recalls are disabled. this allows the user to interactively test their modules by writing the dac value for modulation. the output is updated with the new value at the end of the write cycle. the i _ c stop condition is the end of the write cycle. 1 = enables auto control of the lut for modulation (default). bit1 apc-en: 0 = apc dac is write-able by the user and the lut recalls are disabled. this allows the user to interactively test their modules by writing the dac value for apc reference. the output is updated with the new value at the end of the write cycle. the i _ c stop condition is the end of the write cycle. 1 = enables auto control of the lut for apc reference (default). bit0 bias-en: 0 = bias dac is controlled by the user and the apc is open loop. the bias dac value is written to the man ibias register. all values that are written to man ibias and are greater than the max ibias register setting are not updated and will set the max ibias alarm bit. the bias dac register will continue to reflect the value of the bias dac. this allows the user to interactively test their modules by writing the dac value for bias. the output is updated with the new value at the end of the write cycle to the man ibias register. the i 2 c stop condition is the end of the write cycle. 1 = enables auto control for the apc feedback (default). table 02h, registers
DS1863 burst-mode pon controller with integrated monitoring 44 ____________________________________________________________________ table 02h, register 81h: tindex factory default 00h read access pw2 write access pw2 and (aen = 0) memory type volatile 81h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 holds the calculated index based on the temperature measurement. this index is used for the address during look-up of tables 04h and 05h. for table 04h, the exact address as the value of tindex is used. for table 05h the address used is calculated as follows table 02h, register 82h: mod dac factory default 00h read access pw2 write access pw2 and (mod-en = 0) memory type volatile 82h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the digital value used for vmod and recalled from table 04h at the adjusted memory address found in tindex. the address used is calculated as follows this register is updated at the end of the temperature conversion. tindex h h ? + 80 2 80 tindex temperature c c h = + + 40 2 80 tindex = + temp h 40 2 table 02h, register 83h: apc dac factory default 00h read access pw2 write access pw2 and (apc-en = 0) memory type volatile 83h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the digital value used for apc reference and recalled from table 05h at the memory address found in t index . this register is updated at the end of the temperature conversion.
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 45 table 02h, register 84h to 85h: bias dac factory default 00 00h read access pw2 write access pw2 and (bias-en = 0) memory type volatile 84h 002 12 2 11 2 10 2 9 2 8 2 7 85h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the digital value used for ibias. table 02h, register 86h: device id factory default 63h read access pw2 write access n/a memory type rom 86h 01100011 bit7 bit0 hard wired to show device id. table 02h, register 87h: device ver factory default device version read access pw2 write access n/a memory type rom 87h device version bit7 bit0 hard wired connections to show device version.
DS1863 burst-mode pon controller with integrated monitoring 46 ____________________________________________________________________ table 02h, register 88h: update rate factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) defines the update rate for comparison of apc control. 88h 0 0 0 0 sr(3:0) bit7 bit0 bit7:4 0 bit3:0 sr(3:0) : 4-bit update rate for comparison of apc control. sr 3 sr 0 minimum time from ben to first sample (t first ) 50ns repeated sample period following first sample (t rep ) 0000b 350ns 800ns 0001b 550ns 1200ns 0010b 750ns 1600ns 0011b 950ns 2000ns 0100b 1350ns 2800ns 0101b 1550ns 3200ns 0110b 1750ns 3600ns 0111b 2150ns 4400ns 1000b 2950ns 6000ns 1001b* 3150ns 6400ns * all codes greater than 1001b (1010b?11b) use the maximum sample time of code 1001b.
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 47 table 02h, register 8ah: startup step factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) 8ah 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 bit7 bit0 this value will define the maximum allowed step for the upper 8 bits of ibias output during start-up. table 02h, register 89h: config factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) 89h fe tg d ir tx - f e n re s e rv e d as e l re s e rv e d re s e rv e d re s e rv e d re s e rv e d bit7 bit0 configure the memory location and the polarity of the digital outputs. bit7 fetg dir: chooses the direction or polarity of the fetg output for normal operation. 0 = under normal operation, fetg will be pulled low. (default) 1 = under normal operation, fetg will be pulled high. bit6 tx-f en: 0 = the alarm bits will immediately reflect the status of the last comparison. (default) 1 = the alarm bits are latched until cleared by a tx-d transition or power-down. if v cc low alarm is enabled for either fetg or tx-f then latching is disabled until after the first v cc measurement is made above the v cc to set-point to allow for proper operation during slow power-on cycles. bit5 reserved bit4 asel: address select. 0 = device address of a2h (default). 1 = device-address is equal to the value found in byte device_address (table 02h, 8ch). bit3:0 reserved
DS1863 burst-mode pon controller with integrated monitoring 48 ____________________________________________________________________ table 02h, register 8bh: mod ranging factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) 8bh reserved reserved reserved reserved reserved mod 2 mod 1 mod 0 bit7 bit0 the lower nibble of this byte controls the full-scale range of the modulation dac bit7:3 reserved (default = 0) bit2:0 mod ranging: 3-bit value to select fs output voltage for v mod . default 0006 and creates a fs of 1.25v. table 02h, register 8ch: device address factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) 8ch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 x bit7 bit0 x = don't care. this value becomes the device address for the main memory when asel (table 02h, 89h) bit is set. mod 2 to mod 0 % of 1.25v fs voltage 000b 100 1.250 001b 80.05 1.001 010b 66.75 0.833 011b 50.13 0.627 100b 40.16 0.502 101b 33.5 0.419 110b 28.75 0.359 111b 25.18 0.315
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 49 table 02h, register 8dh: comp ranging factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) 8dh reserved reserved reserved reserved reserved apc 2 apc 1 apc 0 bit7 bit0 this byte controls the full-scale range for the quick-trip monitoring of the apc reference as well as the closed loop monitorin g of apc. bit7:3 reserved (default = 0) bit2:0 apc ranging: 3-bit value to select the fs comparison voltage for bmd with the apc. default is 000b and creates a fs voltage of 2.5v. table 02h, register 8eh: right shift 1 factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) 8eh reserved mon1_2 mon1_1 mon1_0 reserved mon2_2 mon2_1 mon2_0 bit7 bit0 allows for right-shifting the final answer of mon1 and mon2 voltage measurements. this allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct lsb. apc 2 to apc 0 % of 2.5v fs voltage 000b 100 2.500 001b 80.07 2.002 010b 66.79 1.670 011b 50.18 1.255 100b 40.22 1.006 101b 33.57 0.839 110b 28.82 0.721 111b 25.26 0.632
DS1863 burst-mode pon controller with integrated monitoring 50 ____________________________________________________________________ table 02h, register 8fh: right shift 0 factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) 8fh reserved mon3_2 mon3_1 mon3_0 reserved reserved reserved reserved bit7 bit0 allows for right-shifting the final answer of mon3 voltage measurements. this allows for scaling the measurements to the smalle st full-scale voltage and then right-shifting the final result so the reading is weighted to the correct lsb. table 02h, register 90h to 91h: reserved factory default: 0000h read access pw2 write access pw2 memory type: nonvolatile (see) these registers are reserved. table 02h, register 92h to 93h: v cc scale factory calibrated read access pw2 write access pw2 memory type nonvolatile (see) 92h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 93h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 controls the scaling or gain of the v cc measurements. the factory-calibrated value will produce a fs voltage of 6.5536v.
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 51 table 02h, register 94h to 95h: mon1 scale table 02h, register 96h to 97h: mon2 scale table 02h, register 98h to 99h: mon3 scale factory calibrated read access pw2 write access pw2 memory type nonvolatile (see) 94h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 95h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 96h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 97h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 98h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 99h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 controls the scaling or gain of the mon1, mon2, and mon3 measurements. the default hexadecimal value will correspond to 2.5v. the factory-calibrated value will produce a fs voltage of 2.5v. table 02h, register 9ah to a1h: reserved factory default 0000h read access pw2 write access pw2 memory type nonvolatile (see) these registers are reserved. table 02h, register a2h to a3h: v cc offset factory default 0000h read access pw2 write access pw2 memory type nonvolatile (see) a2h ss2 15 2 14 2 13 2 12 2 11 2 10 a3h 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit7 bit0 allows for offset control of v cc measurement if desired.
DS1863 burst-mode pon controller with integrated monitoring 52 ____________________________________________________________________ table 02h, register a4h to a5h: mon1 offset table 02h, register a6h to a7h: mon2 offset table 02h, register a8h to a9h: mon3 offset factory default 0000h read access pw2 write access pw2 memory type nonvolatile (see) a4h ss2 15 2 14 2 13 2 12 2 11 2 10 a5h 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 a6h ss2 15 2 14 2 13 2 12 2 11 2 10 a7h 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 a8h ss2 15 2 14 2 13 2 12 2 11 2 10 a9h 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit7 bit0 allows for offset control of mon1, mon2, and mon3 measurement if desired. table 02h, register aah to adh: reserved factory default 0000 0000h read access pw2 write access pw2 memory type nonvolatile (see) these registers are reserved. table 02h, register aeh to afh: temp offset factory calibrated read access pw2 write access pw2 memory type nonvolatile (see) aeh s2 8 2 7 2 6 2 5 2 4 2 3 2 2 afh 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 bit7 bit0 allows for offset control of temp measurement if desired. the final result must be xor ed with bb40h before writing to this register. factory calibration contains the desired value for a reading of the temperature in degrees celcius.
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 53 table 02h, register b0h to b3h: pw1 factory default ffff ffffh read access n/a write access pw2 memory type nonvolatile (see) b0h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 b1h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 b2h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 b3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the pwe value is compared against the value written to this location to enable pw1 access. at power-on, the pwe value is set to all ones. thus writing these bytes to all ones grants pw1 access on power-up without writing the password entry. all reads of this register are 00h. table 02h, register b4h to b7h: pw2 factory default ffff ffffh read access n/a write access pw2 memory type nonvolatile (see) b4h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 b5h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 b6h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 b7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the pwe value is compared against the value written to this location to enable pw2 access. at power-on, the pwe value is set to all ones. thus writing these bytes to all ones grants pw2 access on power-up without writing the password entry. all reads of this register are 00h.
DS1863 burst-mode pon controller with integrated monitoring 54 ____________________________________________________________________ table 02h, register b8h: fetg enable 1 factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) b8h te m p e n v c c e n m on 1 e n m on 2 e n m on 3 e n re s e rv e d re s e rv e d re s e rv e d bit7 bit0 configures the maskable interrupt for the fetg pin. bit7 temp en: enables/disables active interrupts on the fetg pin due to temperature measurements outside the threshold limits. 0 = disable (default) 1 = enable bit6 v cc en: enables/disables active interrupts on the fetg pin due to v cc measurements outside the threshold limits. 0 = disable (default) 1 = enable bit5 mon1 en: enables/disables active interrupts on the fetg pin due to mon1 measurements outside the threshold limits. 0 = disable (default) 1 = enable bit4 mon2 en: enables/disables active interrupts on the fetg pin due to mon2 measurements outside the threshold limits. 0 = disable (default) 1 = enable bit3 mon3 en: enables/disables active interrupts on the fetg pin due to mon3 measurements outside the threshold limits. 0 = disable (default) 1 = enable bit2:0 reserved (default = 0)
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 55 table 02h, register b9h: fetg enable 0 factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) b9h tx p - h i e n tx p - lo e n bias - h i e n bias m ax e n re s e rv e d re s e rv e d re s e rv e d re s e rv e d bit7 bit0 configures the maskable interrupt for the fetg pin. bit7 tx-p-hi en: enables/disables active interrupts on the fetg pin due to tx-p fast comparisons above the threshold limit. 0 = disable (default) 1 = enable. bit6 tx-p-lo en: enables/disables active interrupts on the fetg pin due to tx-p fast comparisons below the threshold limit. 0 = disable (default) 1 = enable bit5 bias-hi en: enables/disables active interrupts on the fetg pin due to bias fast comparisons above the threshold limit. 0 = disable (default) 1 = enable bit4 bias max en: enables/disables active interrupts on the fetg pin due to bias fast comparisons below the threshold limit. 0 = disable (default) 1 = enable bit3:0 reserved (default = 0)
DS1863 burst-mode pon controller with integrated monitoring 56 ____________________________________________________________________ table 02h, register bah: tx-f enable 1 factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) bah te m p e n v c c e n m on 1 e n m on 2 e n m on 3 e n re s e rv e d re s e rv e d re s e rv e d bit7 bit0 configures the maskable interrupt for the tx-f pin. bit7 temp en: enables/disables active interrupts on the tx-f pin due to temperature measurements outside the threshold limits. 0 = disable (default) 1 = enable bit6 v cc en: enables/disables active interrupts on the tx-f pin due to v cc measurements outside the threshold limits. 0 = disable (default) 1 = enable bit5 mon1 en: enables/disables active interrupts on the tx-f pin due to mon1measurements outside the threshold limits. 0 = disable (default) 1 = enable bit4 mon2 en: enables/disables active interrupts on the tx-f pin due to mon2 measurements outside the threshold limits. 0 = disable (default) 1 = enable. bit3 mon3 en: enables/disables active interrupts on the tx-f pin due to mon3 measurements outside the threshold limits. 0 = disable (default) 1 = enable bit2:0 reserved (default = 0)
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 57 table 02h, register bbh: tx-f enable 0 factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) bbh tx p - h i e n tx p - lo e n bias - h i e n bias m ax e n re s e rv e d re s e rv e d re s e rv e d fe tg e n bit7 bit0 configures the maskable interrupt for the tx-f pin. bit7 txp-hi en: enables/disables active interrupts on the tx-f pin due to tx-p fast comparisons above the threshold limit. 0 = disable (default) 1 = enable. bit6 txp-lo en: enables/disables active interrupts on the tx-f pin due to tx-p fast comparisons below the threshold limit. 0 = disable (default) 1 = enable bit5 bias-hi en: enables/disables active interrupts on the tx-f pin due to bias fast comparisons above the threshold limit. 0 = disable (default) 1 = enable bit4 bias max en: enables/disables active interrupts on the tx-f pin due to bias fast comparisons above the threshold limit. 0 = disable (default) 1 = enable bit3:1 reserved (default = 0) bit0 fetg en: 0 = normal fetg operation (default) 1 = enables fetg to act as an input to tx-f output.
DS1863 burst-mode pon controller with integrated monitoring 58 ____________________________________________________________________ table 02h, register bch: htxp factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) bch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 fast comparison dac adjust for high txp. this value is added to the apc_dac value recalled from table 04h. if the sum is greate r than 0xff then 0xff is used. comparisons greater than apc_dac plus this value, found on the bmd pin, will create a tx-p hi alarm. table 02h, register bdh: ltxp factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) bdh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 fast comparison dac adjust for low txp. this value is subtracted from the apc_dac value recalled from table 04h. if the difference is less than 0x00 then 0x00 is used. comparisons less than apc_dac minus this value, found on the bmd pin, will create a tx-plo alarm. table 02h, register beh: hbias factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) beh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 fast comparison dac setting for high bias.
DS1863 burst-mode pon controller with integrated monitoring ____________________________________________________________________ 59 table 02h, register c0h to f7h: empty table 02h, register f8h f9h: man ibias factory default: 00h read access pw2 write access pw2 and (bias-en = 0) memory type: volatile f8h reserved reserved 2 12 2 11 2 10 2 9 2 8 2 7 f9h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 when bias-en (table 02h, 80h) is written to 0, writes to these bytes will control the lower portion of the ibias dac [7:0]. table 02h, register fah: man_cntl factory default: 00h read access pw2 write access pw2 and (bias-en = 0) memory type: volatile fah reserved reserved reserved reserved reserved reserved reserved man_clk bit7 bit0 when bias-en bit (table 02h, 80h) is written to zero, bit zero of this byte will control the updates of the man ibias value to the bias output. the values of man ibias should be written with a separate write command. setting bit zero to a 1 will clock the man ibias value to the output dac. 1. write the man ibias value with a write command. 2. set the man clk bit to a 1 with a separate write command. 3. clear the man clk bit to a 0 with a separate write command. table 02h, register bfh: max ibias factory default: 00h read access pw2 write access pw2 memory type: nonvolatile (see) bfh 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 bit7 bit0 thi s val ue w i l l d efi ne the m axi m um d ac val ue al l ow ed for the up p er 8 b i ts of ibias outp ut d ur i ng al l op er ati ons. d ur i ng the i ni ti al step and b i nar y sear ch, thi s val ue w i l l not cause an al ar m b ut w i l l sti l l cl am p the ibias d ac outp ut. after the star tup seq uence ( or nor m al ap c op er ati ons) , i f the ap c l oop tr i es to cr eate an ibias val ue g r eater than thi s setti ng , ibias i s cl am p ed , and cr eates a bias m ax al ar m . s etti ng s 00h thr oug h fe h ar e i ntend ed for nor m al ap c m od e of op er ati on. s etti ng ffh i s r eser ved for m anual ibias m od e.
DS1863 burst-mode pon controller with integrated monitoring 60 ____________________________________________________________________ table 02h, register fbh to ffh: reserved factory default read access write access memory type: these registers are reserved. table 03h, register 80h to ffh: pw2 eeprom factory default 00h read access pw2 write access pw2 memory type: nonvolatile (ee) 80h-ffh ee ee ee ee ee ee ee ee bit7 bit0 pw2 general-purpose eeprom. table 04h, register 80h to c7h: modulation lut factory default 00h read access pw2 write access pw2 memory type: nonvolatile (ee) 80h-c7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the unsigned value for modulation dac output. the modulation lut is a set of registers assigned to hold the temperature profile for the modulation dac. the values in this ta ble combined with the mod bits in the mod ranging register (table 02h, register 8bh) determine the set point for the modulation voltage. the temperature measurement is used to index the lut (t index, table 02h, register 81h) in 2 c increments from -40 c to +102 c, starting at 80h in table 04h. register 80h defines the -40 c to -38 c mod output, register 81h defines -38 c to -36 c mod output, and so on. values recalled from this eeprom memory table are written into the mod dac location which holds the value until the next temperature conversion. the part can be placed into a manual mode (mod_en bit, table 02h, register 80h), where mod dac can be directly controlled for calibration. if the temperature compensation functionality is not required, then program the entire table 04h, to the desired modulation setting. table 03h, register descriptions table 04h, register descriptions
DS1863 burst-mode pon controller with integrated monitoring table 05h, register 80h to c7h: apc tracking error lut factory default 00h read access pw2 write access pw2 memory type: nonvolatile (ee) 80h-a3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the tracking error lut is set of registers assigned to hold the temperature profile for the apc reference dac. the values in th is table combined with the apc bits in the comp ranging register (table 02h, register 8dh) determine the set point for the apc loo p. the on board temperature measurement is used to index the lut (t index, table 02h, register 81h) in 4 c increments from -40 c to +100 c, starting at register 80h in table 05h. register 80h defines the -40 c to -36 c apc reference value, register 81h defines -36 c to -32 c apc reference value, and so on. values recalled from this eeprom memory table are written into the apc dac location, which holds the value until the next temperature conversion. the part can be placed into a manual mode (apc_en bit, table 02h, register 80h), where apc dac can be directly controlled for calibration. if tracking error temperature compensation is not required by the application, program the entire lut to the apc set-point. table 05h, register a3h to a7h: reserved factory default read access write access memory type: these registers are reserved. table 05h, register descriptions package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo . maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 61 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. springer

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